Control of operator position display

ABSTRACT

A display buffer for controlling lighting of lamps and other functions at a plurality of operator positions. There is an arrangement of relay drivers and relays into what are effectively matrix circuits, with current sensors connected to relay driver ground switches using a common resistor for each bit of status codes (including reset), so that current for only one relay should flow through each resistor. The arrangement includes logic associated with the current sensors to monitor the operation and detect failures.

United States Patent 1191 Bieszczad et al.

COMMAND MESSAGE FROM DATA LlNK RECEIVER CONTROL OF OPERATOR POSITION DISPLAY lnventors: Edward S. Bieszczad, Hoffman Estates; William R. Wedmore, Glen Ellyn; John S. Young, Addison, all of I11.

GTE Automatic Electric Laboratories Incorporated, Northlake, 111.

Filed: Sept. 14, 1973 Appl. No.2 397,570

Assignee:

US. Cl. 340/334, 179/27 FF, 340/248 A, 340/332 Int. Cl. G08b 5/36 Field of Search 340/334, 248 A, 332; 179/27 FF References Cited UNITED STATES PATENTS 5/1964 Bonanno 179/27 FF POSITION DECODE CONTROL GROUP DECODE 1 Sept. 10, 1974 3,341,661 9/1967 Curtis 179/27 1=1= 3,341,816 9/1967 Davis et al. 340/248 A 3,594,778 7/1971 Herald et al..... 340/334x 3,634,665 1/1972 Carter et a1 ..s4o/332x Primary Examiner-David L. Trafton [57] ABSTRACT A display buffer for controlling lighting of lamps and other functions at a plurality of operator positions. There is an arrangement of relay drivers and relays into what are effectively matrix circuits, with current sensors connected to relay driver ground switches using a common resistor for each bit of status codes (including reset), so that current for only one relay should flow through each resistor. The arrangement includes logic associated with the current sensors to monitor the operation and detect failures.

5 Claims, 18 Drawing Figures B12 TEST 1 PATENIEUSEPIOIBN 3.835.466

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Emmmno 53% 9 omkmOIm CONTROL OF OPERATOR POSITION DISPLAY BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a display buffer for controlling lighting of lamps and other functions at a plurality of operator positions.

2. Description of the Prior Art A display buffer is described in the Bell System Technical Journal, Vol. 49, No. 10, Dec. 1970, pages 2,602-2,603.

SUMMARY OF THE INVENTION The invention relates to the arrangement of the relay drivers and relays into what are effectively matrix circuits, with current sensors-connected to relay driver ground switches using a common resistor for each bit of status codes (including reset), so thatcurrent for only one relay should flow through each resistor. The arrangement includes logic associated with the current sensors to monitor the operation and detect failures.

CROSS REFERENCE TO RELATED APPLICATIONS This invention is included in a TSPS system briefly described in the GTE Automatic Electric Technical Journal, Vol. 12, No. 7, July l97l, pages 276-285.

The central processor and peripheral controller are disclosed in a US. Pat. application for Control Complex for TSPS Telephone System, by E. F. Brenski et al., Ser. No. 289,718 filed Sept. 15, 1972.

The data link for communication of data between operators positions and central control is disclosed in a US. application by M. Winn, W. R. Wedmore, and J. S. Young for Data Link Arrangement with Error Checking and Retransmission Control (H-l7l3), Ser. No. 397,454 filed the same day as this application.

DESCRIPTION OF THE DRAWING FIGS. 10-18 are wave form diagrams for operation of the current sensors and associated logic.

DETAILED DESCRIPTION As described in the copending data link patent application, the data link has a local terminal at a base location, and a remote terminal at a traffic office which has a maximum of 62 operator positions. Messages received at the remote terminal include a command data with bits B0-Bl5. A display buffer comprises relays having contacts connected to lamps of the positions. A buffer control circuit is connected between the data set and the display buffer.

The function of the Buffer Control Circuit (BCC) is to accept commands from the RTC (Remote Terminal Circuit), decode then and generate appropriate control signals as required to perform the desired Traffic Office function. In addition, maintenance circuits are pro-' vided to test for the successful completion of most commands to the T0. The functional and maintenance circuits will be discussed separately.

FUNCTIONAL CIRCUITS The structure of the incoming commands is basic to the understanding of the BCC. The command consists of 16 bits divided into three fields. The position field (Bits (I) through 5), the control group field (Bits 6 through 11) and the status code field (Bits 12 through 15).

The Position Field, B through B5, identifies the position to which the command is addressed with Ed) as the most significant bit. These positions consists of the 62 TSPS Positions numbered I through 62 and two psuedo-positions numbered and 63. Commands to position (1 control the MRG (Maintenance Report Generator) at present; while commands to position 63 control the displays on the administrative cabinets and perform all non-TSPS position control functions in the TO. other than the MRG. If they should be required position qb commands could perform additional T.O. control functions.

The control group field, B6 through B11, usually identifies the control group addressed which is associated with the position or psuedo-position addressed in B4) through B5. A control group number is binary coded with B6 as the most significant digit. It identifies a set of one or more devices, usually lamps, grouped together for coding efficiency because they can only take on a limited number of states. In most cases a control group consists of a set of lamps only one of which can be lit at any given time. All of the control groups and their functions are shown in Tables 1 through 3. Table 1 shows the control group functions for position qbd), the MRG. Table 2 shows the control groups for Trafiic Service Positions, numbered 1 through 62, and Table 3 shows the control groups for Position 63, the Administrative Cabinet Circuit.

The remaining four bits of the command, B12 through B15, the status code field, describe the state desired for the control group. The number of states which any individual control group can take varies between 1 and 13. These are listed in Tables 1 through 3 as subdivisions of the control group functions. In addition to providing for control of a traffic office with the commands listed in Tables 1 through 3 the BCC can be used as a service observation system controller. For control groups which require more than eight states all four bits of the status field are used. If only 3 bits are required then bits B12 through B14 are used. If two bits, then B12 and B13. Two state control groups only use B12. In general, zeros in the status code indicates reset the control group. The only exceptions to the rule are control groups 64 and 61 in the Service Observing application.

As shown in FIG. 1, the buffer control circuit BCC is basically a decoding device for the incoming command fields. It is implemented with I-ITL logic and with Main Ground Switch and Main Battery Switch Discrete Printed Circuit Boards. As can be seen in FIG. I, the position field is used to drive a one of 64 position decoder generating 64 PD (Position Decode) leads. Since the decoder generates an inverted signal, the PD leads are inverted before being applied to the position drivers. The position drivers are gates B (Main Battery Switches) which switch battery to the output identified .in the position field. The position decoder is enabled by DREN is further discussed with maintenance circuits later in this section.

The second field, the control group field, is initially handled in the same manner as the position field. B6 through B11, drive a one of 64 decoder identical to the position field decoder. The decoded outputs, called CG (ControlGroup) leads, are then inverted.

The status code field provides a second source of inputs to the relay driver logic gates. This field again needs to be buffered. In addition, at the buffering stage all zeros in the field (Reset) is detected and brought out as a separate signal, RST. In the Traffic Office application, RST. plus the individual bits, B12 through B15, provide all of the inputs other than the CG leads required for the relay driver logic gates. The output of the relay driver logic gates in turn drives the FS (Function Select) relay drivers G which are (Main Ground Switches) which apply grounds at the FS outputs selected bythe relays driver logic. This coincidence of battery from the position field and grounds from the remaining fields will then pull-in l-IQA relays in the buffer. The circuits of the main battery switches B and main ground switches G are shown in FIGS. 2 and 3.

Note that'the ground switch output is connected via a current sensor to ground. This output is shown at the bottom of each switch G in FIG. 1.

Almost. all control functions at the T0. are performed using the PS and FS signal coincidence as described above. There are however three other control interfaces which are different. The first of these is the TMBC control. Here the position field is used to drive MBS switches with outputs RBO through RBS which then store the position field in an HQA relay register.

REGRST, also a battery switch, is used to reset a relay I register. MON and TSTwhich are the outputs of ground switches driven by CG44 and CG43 respectively to select one of two registers. The logic inputs necessary to energize the outputs are shown in Table 6. Secondly, there is the RECON-TBLRST logic which provides switched ground on either of the two output leads to control switchover of copies of TOCF. Its logic equation is also shown-in Table 6. RCT.CR is the command relay (CR) lead from the data set indicating completion of receipt of message. Finally there are the PSF and RRF leads. Their logic equations are also shown in Table 6. Their output is I-ITL logic levels. PSF (Position Status Flag) directed to the Key Scanner requests the contents of the key bus of the position identified in the position field. RRF directed to the remote terminal circuit requests retransmission of the message with sequence number in B13 through B15.

DISPLAY BUFFER tery potential is supplied via lead PS0] to all five relays and also to relays of other groups for the same position. As shown in Table 2, a digit display message may have any value from 1 to 0, with bits B12-B15 coded accordingly. When the decoders in FIG. 1 are activated, the selected relays operate, and make before break contacts (formD'indicated by disconnect them from the driver leads and lock over a circuit including break contacts of the reset relay. A decoding contact'tree connection via make contacts of the function relays to ground. The function relays restore, which then restores the release relay.

The release relay for this group is also used to release the function relays of groups 213 and 42. The locking path for the release relay therefore has parallel connected make contacts on all the function relays of these groups. Because of the number of relays in these groups, the release relay has two break contacts for locking the function relays.

FIG. 5 shows the relays of control group 25, position 1, which control a key calling lamp. As shown in Table 2, the lamp may be lit steady with bit B13, or flashing with bits B12 and B13. For flashing, relay MA (bit B12) transfers the battery connection to a IPM source.

BCC MAINTENANCE CIRCUITS The BCC maintenance circuits comprise current sensors and associated logic. The function of the Current Sensor and associated logic is to determine that proper relay operation occurred in the Display Buffer Circuit, a 62 by 141 relay matrix. It accomplishes this by monitoring the current switched by the Function Select MGS circuits, the verticals of the 'DBCF matrix. Because it is possible for as many as four relays to pull-in at once and as few as one and because the reset relays function differently from the others, the current sensor circuits are subdivided into five separate similar subsystems. One each forthe relays associated with Bits B12 through B15 of the command and one for reset relays. We can then conceive of the DBCF matrix as being five submatrices organized so that on any given command at most one and only one relay in each submatrix should pull-in.

System operation can be divided into Current Sensing and trouble detecting by current Sensor Logic. The current sensing circuit is shown on FIG. 6. On an incoming command to a position the appropriate position main battery switch and one of the Function Select main ground switches are switched on. The current pulling in the relay will flow through the emitters of the main ground switches which gets ground through the 10 ohm register, R1, which also provides ground to the emitters of all the other B12 main ground switches output transistors.

The voltage generated across R1 is coupled via C1 of FIG. 6 to a pair of differential amplifiers used as voltage comparators. The low threshold detector has Reference Voltage 0.13 volts and its output switches from logic (I: 11) volts) to logic 1 (+12 volts) when the voltage across R1 is greater than the reference voltage. The high threshold detector switches from logic (1) to 1 when the voltage across R1 is greater than the reference voltage 0.38 volts. Minus 0.13 volts corresponds to 13MA through R1 while 0.38 volts means 38MA. All five current sensor subsystems have identical current sensors.

The logic itself can be subdivided into common logic (FIG. 7), B12 through B15 logic (FIG. 8) and Reset logic (FIG. 9). The current Sensor Logic, can best be understood by considering the waveforms across R1 for normal operation and the various failure modes anticipated. FIG. shows typical waveforms across R1 for normal pull-in in the B12 submatrix based on tests with I-IQA relays. The figure also shows CR (Command Ready) a nominal MS pulse during which pull-in is required and all other relevant gates and FFs in the logic. The B12 Current Sensor logic FIG. 8 contains four SR flip-flops (latches) and control gates. The flipflops are the Inhibit FF, the Normal I FF, the IRZ FF and the CS Trouble FF. In normal operation only the Normal I and the IRZ FF are affected.

The sequence of events after a command with a B12 pull-in arrives is then as follows:

1. The initializing pulse INITIALIZE, resets the Normal I FF and the IRZ FF at the beginning of a command sequence. The initializing pulse is generated by the l-ITL monostable in the CS Common Logic shown in FIG. 7 whenever Command Ready (CR has a positive swing. It resets the Normal I FF and the IRZ FF of all five current sensors logic. Unless a failure occurred on the previous operation both .of these flip-flops should be set at the begin ning of a command. The waveforms for this and succeeding steps is shown in FIG. 11.

2. The voltage across R1 begins to rise exponentially eventually reaching 130 MV and switching AMPl output CSlOUTL to l.

3. CSlOUTL is buffered by the two input NANDS 9 and 11 of FIG. 9. The buffering is necessary because the op amp will only drive 2 HTL logic loads. CSIOUTL is gated by CSEN (current sensor enable), a 2 millisecond pulse which suppresses CSlOUTL as well as all other voltage comparator outputs until switching transients have died down.

4. B12.CS1OUTL is formed at gate 21. The function of this gate is to determine that a relay should be pulled in, B12 l, and that it did pull-in, CSlOUTL l.

5Proper pull-in as indicated in four next drives a 3- input OR formed of gates 17, 19 and 1. The other inputs to this OR will be discussed subsequently as other normal modes of Current Sensor logic operation.

6. The output of the OR is next NANDED in gate 13 with Command Ready (CR) to set the NORMAL I FF, gates 16 and 15. The Normal I FF stores the information that the voltage across R1 exceeded 130 volts, i.e., that the current drawn by the MGSs exceeded 13 MA.

7. The voltage across R1 continues to rise until the relay pulls in at 250 MV i 50 as measured in tests with I-IQA relays. At pull-in the voltage across R1 drops to zero as ground comes back through the NC contact during the bunching period of the form D contact. At this time CSlOUTL drops back to zero. The output of gate 9 goes to 12 volts which when NANDED with Normal I FF in gate 3 and switches on the IRZ FF, gates 18 and 20. IRZ is a mnemonic for Current Returned to Zero.

8. Nothing of further significance occurs through the end of CR (Command Ready) and the 416 [LS period of CR until INITIALIZE occurs at the next positive swing of Command Ready, starting another sequence. If no B12 submatrix relays are to be pulled in the waveforms will be as shown in FIG. 10.

After the form D contact bunching period the relay is isolated from the MGS and MBS. Since the MGS is not turned off for B12 through B15 current sensors during the remainder of CR, the leakage current through the 30K resistor in the MGS shown on FIG. 6 will draw approximately 1.5 MA. causing the 1.5 MV drop across R1. This is not enough to switch AMP] and should have no further effect. The MGS and MBS are left on to test for shorted diodes as described later.

The other normal modes of operation are necessitated by the operation of the IRZ FF. In order to insure that pull-in occurred the IRZ FF must be set before CR drops back to zero. If it is not set gate 26 will switch to zero and set the failure flip-flop, gates 4 and A of FIG. 9 via one of the three remaining inputs to A used as a S-input trouble OR." The commonest example of a command which would have this difficulty with the IRZ FF is one where B12 d) as shown in FIG. 11. In this case none of the B12 relays should pull in. The B12 input at gate 17 in this event will simulate normal I and set the NORMAL I FF when CR comes up. Since no MGS should be turned on in this case, CSlOUTL should be d) and the IRZ FF should also be set immediately afterwards.

The third input which sets the Normal I FF is C- SINH. This signal which originates in the CS Common Control logic FIG. 7 is a 7 input OR which indicates a message to T.O. Hardware for subsystems other than the Display buffer matrix or a dummy message. These other subsystems are the TMBC (MON or TST), the KSC (PSF or RRF) and SSC (RECON and TBLRST). Key waveforms for this case are shown in FIG. 12.

There are four fault conditions which will set the Current Sensor Trouble FF. These are:

1. Failure to set the IRZ FF during the 20 MS.CR period as detected by gate 26. Display Buffer Fault conditions which could cause this are:

a. Open output in activated MGS or MBS which would never allow NORMAL I FF to be set.

b. Open diode or winding at crosspoint relay which would also never allow NORMAL I FF to be set.

0. Active MGS decoder stuck at 1 or Active MBS decoder stuck at d) which would also never allow NORMAL I FF to be set.

d. A stuck armature on crosspoint relay with resulting failure to eventually isolate coil from MGS during Command Ready.

In any of these faults the waveforms in the Current Sensor system will be as shown in FIG. 13.

2. The next two cases are those which set the IN- HIBIT FF, gates 6, 7 and 8. This FF is set up by a two input OR formed from gates 5, 1 and 12. The upper input to the OR is CSlOUTH and its primary function is to detect more than one relay pulling in. The relevant CS system waveforms are shown on FIG. 14. The INHIBIT FF is then reset by CR thereby providing test capability for the next Command. The fact that a failure occurred is stored in the CSIFLR FF through another input to gate A and this failure FF retains the information that a failure occurred until reset by a specific command from base location energizing TBLRST.

Failures which will set CSlOUTI-I are:

l. Shorted output on MGS or MBS other than the one activated.

2. Decoder output for MGS other than one activated stuck at 1 or MSB output other than that activated stuck at d). 3. Shorted turns on crosspoint coil or short in wiring.

The other failure modewhich sets the INHIBIT FF is CS1OUTL-Bl2 l or an attempt to pull in a relay as evidenced by R-l Current greater than 13 MA. when none should be pulled in. The and function is perdiodes in the matrix. This is accomplishedas can be seen in FIG. 16 by detecting the shunt current through the shorted diode during the time remaining after pullin of the intended relay. Another fault which will cause the same output is a buzzing relay, with the current now flowing through the coil to be pulled-in and not through a shunt.

The B13 through B submatrix Current Sensor subsystem are identical to the B12 subsystem except that the matrices themselves are smaller. The RST (Reset) submatrix is different from the previous matrices as described in Section 4, but the difference is only in the latching mechanism as is shown on FIG. 17 and does not effectthe theory of operation. The RST current sensors and their operation is also identical to that of the B12 through B15, but the RST Current Sensor logic is different in two respects. First, as can be seen in the waveforms for a normal RST pull-in in FIG. 17 DREN (Driver Enable) is cut off as shown as'pull-in occurs. This is accomplished by an OR of the INHBIT FF and the IRZ FF in gates 25 and 22. The second difference is that the set lead to the INHIBIT FF is gated by BIGRST. This signal which is generated in the CS. Common logic is an OR OF all the commands which would pull in more than one Reset relay. These commands will be used at the end of a call to reset all called related dis plays. Since this is an additional mode of normal operation the waveforms for this case is shown in FIG. 18. Because the drivers are turned off after pullin, the leakage current observed in the B12 matrix no longer occurs. For this reason also, the shunt current observed in the case of a shorted diode will not occur when pulling in crosspoints of the RST matrix. This is not a serious disability since as shown in FIG. 14 in order to detect the shunt current through the shorted diode it is necessary to pull in a crosspoint with different horizontal and vertical from the defective diode.

This can be accomplished in the B12 through B15 submatrices to test RST crosspoint diodes. The I after IRZ gate is still retained in the RST CS5 logic but its sole function is to detect a buzzing RST relay.

In addition to detecting component failures, the current sensors and logic can be used to interrogate the DBCF and determine the status of crosspoints. This is done by sending a pull in message to each crosspoint immediately followed by a reset of the same crosspoint. If the crosspoint was not latched initially, both of these operations will appear normal. However, if it was latched a trouble message will be generated because 8 CSIOUTL will never occur and the NORMAL I and consequently the IRZ FFs will never be set.

TABLE 1 CPU COMMANDS FOR POSITION d) (MRG) CONTROL CONTROL STATUS GROUP GROUP CODE NUMBER CODE BIZ-BIS B6Bl 1 FUNCTION Remove Alarm l, TOCF Current Sensor l Failure, from MRG Key bus. Remove Alarm 2, TOCFrb Current Sensor 2 Failure, from MRG Key bus. Remove Alarm 3, TOCF Current Sensor 3 Failure.

from MRG Key bus.

Current Sensor 4 Failure, from MRG Key bus. Remove Alarm 5, TOCFdz Current Sensor 5 Failure, from MRG Key bus. Remove Alarm 6, TOCFl Current Sensor 1 Failure, from MRG Key bus. Remove Alarm 7, TOCFI Current Sensor 2 Failure from MRG Key bus. Remove Alarm 8, TOCFI Current Sensor 3 Failure, from MRG Key bus. Remove Alarm 9, TOCFl Current Sensor 4 Failure. from MRG Key bus. Remove Alarm l0, TOCFI Current Sensor 5 Failure, from MRG Key bus. Remove Alarm ll, Invalid BCCd: Reconfigure message, from MRG Key bus. Remove Alarm l2, Invalid BCCI Reconfigure message, from Key bus. Remove Alarm l3, Invalid ECG!) and BCCl Reconfigure message, from MRG Key bus. Remove Alarm l4, Transfer relay failure, from MRG Key bus.

Remove Alarm l5, Modulator Copy 45 Failure, from MRG Key bus. Remove Alarm l6, Modulator Copy 1 Failure. from MRG Key bus. Remove Alarm l7, Demodulator Copy (11 failure, from MRG Key bus. Remove Alarm l8, Demodulator Copy I failure, from MRG Key bus. Remove Alarm l9, TOSF major alarm, from MRG Key 5. Remove Alarm 20, TOSF minor alarm, from MRG Key bus.

Remove Alarm 22, TOCF fuse alann, from MRG Key bus.

Remove Alarm 23, TOCFI fuse alarm, from MRG Key bus.

Remove Alarm 24, TO. major equipment alarm, from MRG Key bus. Remove Alarm 25, TO. major power alarm, from MRG Key bus. Remove Alarm 26, TD. minor equipment alarm, from MRG Key bus. Remove alarm 27, unassigned, from MRG Key Remove Alarm 28, TOCFd request key, from MRG Key bus.

Remove Alarm 4, TOCF 

1. A display buffer and control circuit for operating display devices and performing other functions at a plurality of positions in accordance with commands received on a set of leads, in commands having a format comprising a position field, a control group field, and a status field, each field comprising a plurality of bits with a lead for each bit in said set, there being N bits in the status fiEld; a position decoder having inputs from the leads for the position field and outputs of which one at a time is selected when the decoder is enabled, a plurality of first switch devices equal to the number of positions, each having an input coupled to an individual output of the position decoder, each first switch device being enabled when its position decoder output is selected to supply a first potential to an individual position select lead; a decoding gate having inputs from all N status bit leads and an output to a reset status lead to provide a true signal condition on the reset status lead when all N of the status bits are zero; a control group decoder having inputs from the leads for the control group field and outputs to control group leads of which one at a time is selected when the decoder is enabled; a plurality of second switch devices, each having an enabling input, a source input, and an output to an individual function select lead, the input of each second switch device being coupled to the output of a function select gate having an input from a control group lead and an input from a status lead, organized into N + 1 status groups, all of the second switch devices in the same status group having their function select gates with an input to the same status bit lead, which for one group is the reset status lead, the source leads of all second switch devices being connected to a multiple point, with a resistor connected between the multiple point and a source of second potential, so that a second switch device when enabled supplies the second potential from the source via the resistor to its function select lead; a decode enable lead connected to said position and control group decoders to normally enable them in response to a command ready signal; a plurality of relays for each position organized into control groups, with at least 1 and not more than N function relays in each control group, and normally including also a reset relay, each relay having a winding and contacts, with one end of the winding coupled to a position select lead and the other end coupled via an isolation diode to a function select lead, each function relay having contacts which when the relay is operated disconnect it from the position select and function select leads and connect it to a locking path which includes break contacts of a reset relay usually in the same control group, and the reset relay having contacts which disconnect it from the position select lead and connect it to a locking path which includes make contacts in parallel for all of the function relays of the control group, so that when the reset relay is selected and operates, it releases the function relays and is then itself released when the function relays have restored, contacts of the function relays connected to operate display devices according to a code of the status bits of each control group; an individual current sensor for each said status group coupled to said resistor of its status group to sense the current through the resistor, each current sensor having a high output lead with means to supply a high signal thereon if the current exceeds a first threshold level, and a low output lead with means to supply a low signal thereon if the current exceeds a second lower threshold level, the normal current being as drawn by one relay being between the two threshold levels, and logic means with connections to said output leads of the current sensors to detect and indicate various normal and abnormal conditions.
 2. A circuit as claimed in claim 1, wherein for some control groups no reset relay is provided, and the locking path for the function relays is via break contacts of the reset relay of another control group for the same position.
 3. A circuit as claimed in claim 2, wherein the reset status group of second switch devices includes some for which the function select gate is enabled in accordance with the signal condition on a plurality of control group leads.
 4. A circuit as claimed in claim 3, wherein said logic means includes means to disable certain responses to the reset current sensor for situations in which a plurality of reset relays are operated in response to the same command.
 5. A circuit as claimed in claim 1, wherein the abnormal conditions include some resulting from defective isolation diodes. 